#ifndef __BSP_SRAM_H
#define __BSP_SRAM_H

#include "stm32f1xx.h"

/* Macro Definitions */
// Using NOR/SRAM Bank1.sector3, address bits HADDR[27,26]=10
// For IS61LV25616/IS62WV25616, address line range is A0~A17
// For IS61LV51216/IS62WV51216, address line range is A0~A18

/* FSMC相关参数 定义 
 * 注意: 我们默认是通过FSMC块3来连接SRAM, 块1有4个片选: FSMC_NE1~4
 *
 * 修改SRAM_FSMC_NEX, 对应的SRAM_CS_GPIO相关设置也得改
 */
#define SRAM_FSMC_NEX           3       /* 使用FSMC_NE3接SRAM_CS,取值范围只能是: 1~4 */

/* SRAM基地址, 根据 SRAM_FSMC_NEX 的设置来决定基址地址
 * 我们一般使用FSMC的块1(BANK1)来驱动SRAM, 块1地址范围总大小为256MB,均分成4块:
 * 存储块1(FSMC_NE1)地址范围: 0X6000 0000 ~ 0X63FF FFFF
 * 存储块2(FSMC_NE2)地址范围: 0X6400 0000 ~ 0X67FF FFFF
 * 存储块3(FSMC_NE3)地址范围: 0X6800 0000 ~ 0X6BFF FFFF
 * 存储块4(FSMC_NE4)地址范围: 0X6C00 0000 ~ 0X6FFF FFFF
 */
#define Bank1_SRAM3_ADDR     (0X60000000 + (0X4000000 * (SRAM_FSMC_NEX - 1)))		
#define IS62WV51216_SIZE     0x100000   // 512*16/2bits = 0x100000, 1M bytes
#define PrestoredTest        0

/* Function Declarations */
void FSMC_SRAM_WriteBuffer(uint8_t *pBuffer, uint32_t WriteAddr, uint32_t n);
void FSMC_SRAM_ReadBuffer(uint8_t *pBuffer, uint32_t ReadAddr, uint32_t n);

int rw_8bit_test(void);
int rw_16bit_test(void);
void rw_nByte_test(void);

#if PrestoredTest == 1
void SRAM_Test(void);
#endif
#endif
